// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VRISCV_BOARD.h for the primary calling header

#include "verilated.h"
#include "verilated_dpi.h"

#include "VRISCV_BOARD__Syms.h"
#include "VRISCV_BOARD___024root.h"

#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__ico(VRISCV_BOARD___024root* vlSelf);
#endif  // VL_DEBUG

void VRISCV_BOARD___024root___eval_triggers__ico(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_triggers__ico\n"); );
    // Body
    vlSelf->__VicoTriggered.at(0U) = (0U == vlSelf->__VicoIterCount);
#ifdef VL_DEBUG
    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
        VRISCV_BOARD___024root___dump_triggers__ico(vlSelf);
    }
#endif
}

#ifdef VL_DEBUG
VL_ATTR_COLD void VRISCV_BOARD___024root___dump_triggers__act(VRISCV_BOARD___024root* vlSelf);
#endif  // VL_DEBUG

void VRISCV_BOARD___024root___eval_triggers__act(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___eval_triggers__act\n"); );
    // Body
    vlSelf->__VactTriggered.at(0U) = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel) 
                                      != (IData)(vlSelf->__Vtrigrprev__TOP__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel));
    vlSelf->__VactTriggered.at(1U) = ((IData)(vlSelf->clk) 
                                      & (~ (IData)(vlSelf->__Vtrigrprev__TOP__clk)));
    vlSelf->__Vtrigrprev__TOP__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel 
        = vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm_sel;
    vlSelf->__Vtrigrprev__TOP__clk = vlSelf->clk;
    if (VL_UNLIKELY((1U & (~ (IData)(vlSelf->__VactDidInit))))) {
        vlSelf->__VactDidInit = 1U;
        vlSelf->__VactTriggered.at(0U) = 1U;
    }
#ifdef VL_DEBUG
    if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
        VRISCV_BOARD___024root___dump_triggers__act(vlSelf);
    }
#endif
}

void VRISCV_BOARD___024unit____Vdpiimwrap_get_cpu_pc_TOP____024unit(IData/*31:0*/ pc, IData/*31:0*/ dnpc);
void VRISCV_BOARD___024unit____Vdpiimwrap_get_cpu_inst_TOP____024unit(IData/*31:0*/ inst);
void VRISCV_BOARD___024unit____Vdpiimwrap_halt_TOP____024unit(CData/*0:0*/ is_halt);
void VRISCV_BOARD___024unit____Vdpiimwrap_data_read_TOP____024unit(IData/*31:0*/ raddr, IData/*31:0*/ &data_read__Vfuncrtn);
void VRISCV_BOARD___024unit____Vdpiimwrap_data_write_TOP____024unit(IData/*31:0*/ waddr, IData/*31:0*/ wdata, CData/*7:0*/ wmask);
void VRISCV_BOARD___024unit____Vdpiimwrap_inst_read_TOP____024unit(IData/*31:0*/ raddr, IData/*31:0*/ &inst_read__Vfuncrtn);

VL_INLINE_OPT void VRISCV_BOARD___024root___nba_sequent__TOP__0(VRISCV_BOARD___024root* vlSelf) {
    if (false && vlSelf) {}  // Prevent unused
    VRISCV_BOARD__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    VL_DEBUG_IF(VL_DBG_MSGF("+    VRISCV_BOARD___024root___nba_sequent__TOP__0\n"); );
    // Init
    IData/*31:0*/ __Vfunc_inst_read__4__Vfuncout;
    __Vfunc_inst_read__4__Vfuncout = 0;
    IData/*31:0*/ __Vfunc_data_read__6__Vfuncout;
    __Vfunc_data_read__6__Vfuncout = 0;
    CData/*4:0*/ __Vdlyvdim0__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0;
    __Vdlyvdim0__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 = 0;
    IData/*31:0*/ __Vdlyvval__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0;
    __Vdlyvval__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 = 0;
    CData/*0:0*/ __Vdlyvset__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0;
    __Vdlyvset__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 = 0;
    VlWide<8>/*255:0*/ __Vtemp_hc3a75447__0;
    VlWide<8>/*255:0*/ __Vtemp_h28f5fd68__0;
    VlWide<10>/*319:0*/ __Vtemp_h2154878c__0;
    VlWide<7>/*223:0*/ __Vtemp_h10a86387__0;
    // Body
    __Vdlyvset__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 = 0U;
    VRISCV_BOARD___024unit____Vdpiimwrap_get_cpu_pc_TOP____024unit(vlSelf->debug_wb_pc, 
                                                                   ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[2U] 
                                                                     << 0x1eU) 
                                                                    | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U] 
                                                                       >> 2U)));
    VRISCV_BOARD___024unit____Vdpiimwrap_get_cpu_inst_TOP____024unit(
                                                                     ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[6U] 
                                                                       << 0xdU) 
                                                                      | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
                                                                         >> 0x13U)));
    if (vlSelf->reset) {
        VRISCV_BOARD___024unit____Vdpiimwrap_halt_TOP____024unit(0U);
    } else {
        VRISCV_BOARD___024unit____Vdpiimwrap_halt_TOP____024unit(
                                                                 (1U 
                                                                  & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U] 
                                                                     >> 1U)));
    }
    if (vlSelf->debug_wb_rf_wen) {
        __Vdlyvval__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 
            = vlSelf->debug_wb_rf_wdata;
        __Vdlyvset__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 = 1U;
        __Vdlyvdim0__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0 
            = vlSelf->debug_wb_rf_waddr;
    }
    if (vlSelf->reset) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid = 0U;
    } else {
        if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin) {
            vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid 
                = (1U & (~ (IData)(vlSelf->reset)));
        }
        if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin) {
            vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid 
                = vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid;
        }
    }
    if ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load) 
          | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_store)) 
         & (~ (IData)(vlSelf->reset)))) {
        VRISCV_BOARD___024unit____Vdpiimwrap_data_read_TOP____024unit(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result, __Vfunc_data_read__6__Vfuncout);
        vlSelf->RISCV_BOARD__DOT__data_sram_rdata = __Vfunc_data_read__6__Vfuncout;
        if (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_store) 
             & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid))) {
            VRISCV_BOARD___024unit____Vdpiimwrap_data_write_TOP____024unit(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result, 
                                                                           ((1U 
                                                                             & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                                             ? 0U
                                                                             : 
                                                                            ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[6U] 
                                                                              << 0xcU) 
                                                                             | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                                >> 0x14U))), (IData)(vlSelf->RISCV_BOARD__DOT__data_sram_wmask));
        }
    }
    if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[0U] 
            = (IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                        ? 0ULL : (0x3ffffffffULL & 
                                  (((QData)((IData)(
                                                    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[1U])) 
                                    << 0x20U) | (QData)((IData)(
                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[0U]))))));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[1U] 
            = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                          ? 0ULL : (((QData)((IData)(
                                                     vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U])) 
                                     << 0x3eU) | (((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[3U])) 
                                                   << 0x1eU) 
                                                  | ((QData)((IData)(
                                                                     vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U])) 
                                                     >> 2U))))) 
                << 2U) | (IData)((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                    ? 0ULL : (0x3ffffffffULL 
                                              & (((QData)((IData)(
                                                                  vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[1U])) 
                                                  << 0x20U) 
                                                 | (QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[0U]))))) 
                                  >> 0x20U)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[2U] 
            = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                          ? 0ULL : (((QData)((IData)(
                                                     vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U])) 
                                     << 0x3eU) | (((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[3U])) 
                                                   << 0x1eU) 
                                                  | ((QData)((IData)(
                                                                     vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U])) 
                                                     >> 2U))))) 
                >> 0x1eU) | ((IData)((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                        ? 0ULL : (((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U])) 
                                                   << 0x3eU) 
                                                  | (((QData)((IData)(
                                                                      vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[3U])) 
                                                      << 0x1eU) 
                                                     | ((QData)((IData)(
                                                                        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U])) 
                                                        >> 2U)))) 
                                      >> 0x20U)) << 2U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U] 
            = ((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                  ? 0U : ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                           << 0xcU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[6U] 
                                       >> 0x14U))) 
                << 7U) | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass) 
                           << 2U) | ((IData)((((1U 
                                                & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                ? 0ULL
                                                : (
                                                   ((QData)((IData)(
                                                                    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U])) 
                                                    << 0x3eU) 
                                                   | (((QData)((IData)(
                                                                       vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[3U])) 
                                                       << 0x1eU) 
                                                      | ((QData)((IData)(
                                                                         vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U])) 
                                                         >> 2U)))) 
                                              >> 0x20U)) 
                                     >> 0x1eU)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U] 
            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result 
                << 0x13U) | ((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                ? 0U : (0xfffU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                                                  >> 4U))) 
                              << 7U) | (((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                          ? 0U : ((
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                                                   << 0xcU) 
                                                  | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[6U] 
                                                     >> 0x14U))) 
                                        >> 0x19U)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
            = ((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                  ? 0U : ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U] 
                           << 0x1eU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[1U] 
                                        >> 2U))) << 0x17U) 
               | (((IData)(vlSelf->RISCV_BOARD__DOT__data_sram_wmask) 
                   << 0x13U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result 
                                >> 0xdU)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U] 
            = ((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                  ? 0U : (7U & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                                >> 0x18U))) << 0x17U) 
               | (((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                    ? 0U : ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U] 
                             << 0x1eU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[1U] 
                                          >> 2U))) 
                  >> 9U));
    } else {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[0U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[1U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[2U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U] = 0U;
    }
    if (__Vdlyvset__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf[__Vdlyvdim0__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0] 
            = __Vdlyvval__RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf__v0;
    }
    if (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_exe_valid) 
         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_allowin))) {
        __Vtemp_hc3a75447__0[7U] = ((0xfff00000U & 
                                     ((0x800000U & 
                                       ((~ ((4U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                            | (5U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))) 
                                        << 0x17U)) 
                                      | ((((0x40U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                           | ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb) 
                                              | (4U 
                                                 == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))
                                           ? 1U : (
                                                   ((0x41U 
                                                     == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                    | ((1U 
                                                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                       | (5U 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))
                                                    ? 3U
                                                    : 
                                                   (((0x42U 
                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                     | (2U 
                                                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))
                                                     ? 7U
                                                     : 0U))) 
                                         << 0x14U))) 
                                    | ((IData)(((((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)) 
                                                  << 0x20U) 
                                                 | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2))) 
                                                >> 0x20U)) 
                                       >> 0xcU));
        __Vtemp_h28f5fd68__0[7U] = ((0xff000000U & 
                                     (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__dst_store) 
                                       << 0x1bU) | 
                                      ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb) 
                                         | ((4U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                            | ((1U 
                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                               | ((5U 
                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                  | (2U 
                                                     == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))))) 
                                        << 0x1aU) | 
                                       ((0x2000000U 
                                         & ((~ ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__dst_store) 
                                                | ((0xc0U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                   | ((0xc1U 
                                                       == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                      | ((0xc5U 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                         | ((0xc7U 
                                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                            | ((0xc4U 
                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                               | ((0xc6U 
                                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                  | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall))))))))) 
                                            << 0x19U)) 
                                        | ((0xe1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                           << 0x18U))))) 
                                    | __Vtemp_hc3a75447__0[7U]);
        __Vtemp_h2154878c__0[8U] = (((IData)((((QData)((IData)(
                                                               (((~ 
                                                                  ((5U 
                                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                                   | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4))) 
                                                                 & (0xe1U 
                                                                    != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))
                                                                 ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1
                                                                 : 
                                                                ((0xe1U 
                                                                  == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                                  ? 0U
                                                                  : 
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])))) 
                                               << 0x20U) 
                                              | (QData)((IData)(
                                                                (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)) 
                                                                  & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4)) 
                                                                     & (0xe1U 
                                                                        != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))
                                                                  ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm
                                                                  : 
                                                                 ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)
                                                                   ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2
                                                                   : 
                                                                  ((0xe1U 
                                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                                    ? 
                                                                   (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)
                                                                    : 4U))))))) 
                                     >> 4U) | ((IData)(
                                                       ((((QData)((IData)(
                                                                          (((~ 
                                                                             ((5U 
                                                                               == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                                              | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4))) 
                                                                            & (0xe1U 
                                                                               != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))
                                                                            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1
                                                                            : 
                                                                           ((0xe1U 
                                                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                                             ? 0U
                                                                             : 
                                                                            vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])))) 
                                                          << 0x20U) 
                                                         | (QData)((IData)(
                                                                           (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)) 
                                                                             & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4)) 
                                                                                & (0xe1U 
                                                                                != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))
                                                                             ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm
                                                                             : 
                                                                            ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)
                                                                              ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2
                                                                              : 
                                                                             ((0xe1U 
                                                                               == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                                               ? 
                                                                              (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)
                                                                               : 4U)))))) 
                                                        >> 0x20U)) 
                                               << 0x1cU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[0U] 
            = (IData)((((QData)((IData)(((0x1c0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak)))) 
                        << 0x21U) | (((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall)) 
                                      << 0x20U) | (QData)((IData)(
                                                                  ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall)
                                                                    ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_cf__DOT__mtvec
                                                                    : 0U))))));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[1U] 
            = ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                  ? 0U : vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U]) 
                << 2U) | (IData)(((((QData)((IData)(
                                                    ((0x1c0U 
                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                     & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak)))) 
                                    << 0x21U) | (((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall)) 
                                                  << 0x20U) 
                                                 | (QData)((IData)(
                                                                   ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall)
                                                                     ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_cf__DOT__mtvec
                                                                     : 0U))))) 
                                  >> 0x20U)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[2U] 
            = ((((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)
                  ? 0U : vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U]) 
                >> 0x1eU) | ((IData)((((QData)((IData)(
                                                       vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])) 
                                       << 0x20U) | (QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[0U])))) 
                             << 2U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[3U] 
            = (((IData)((((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])) 
                          << 0x20U) | (QData)((IData)(
                                                      vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[0U])))) 
                >> 0x1eU) | ((IData)(((((QData)((IData)(
                                                        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])) 
                                        << 0x20U) | (QData)((IData)(
                                                                    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[0U]))) 
                                      >> 0x20U)) << 2U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm 
                << 4U) | ((((0xc5U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                            | (0xc7U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                           << 3U) | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt) 
                                      << 2U) | ((IData)(
                                                        ((((QData)((IData)(
                                                                           vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])) 
                                                           << 0x20U) 
                                                          | (QData)((IData)(
                                                                            vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[0U]))) 
                                                         >> 0x20U)) 
                                                >> 0x1eU))));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
            = (((IData)((((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)) 
                          << 0x20U) | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2)))) 
                << 0x14U) | (((IData)(vlSelf->__VdfgTmp_hea37eb48__0) 
                              << 0xfU) | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__alu_op) 
                                           << 4U) | 
                                          (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm 
                                           >> 0x1cU))));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[6U] 
            = (((IData)((((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)) 
                          << 0x20U) | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2)))) 
                >> 0xcU) | ((IData)(((((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)) 
                                       << 0x20U) | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2))) 
                                     >> 0x20U)) << 0x14U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
            = (((IData)((((QData)((IData)((((~ ((5U 
                                                 == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4))) 
                                            & (0xe1U 
                                               != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))
                                            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1
                                            : ((0xe1U 
                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                ? 0U
                                                : vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])))) 
                          << 0x20U) | (QData)((IData)(
                                                      (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)) 
                                                        & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4)) 
                                                           & (0xe1U 
                                                              != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))
                                                        ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm
                                                        : 
                                                       ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)
                                                         ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2
                                                         : 
                                                        ((0xe1U 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                          ? 
                                                         (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)
                                                          : 4U))))))) 
                << 0x1cU) | __Vtemp_h28f5fd68__0[7U]);
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
            = __Vtemp_h2154878c__0[8U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[9U] 
            = ((IData)(((((QData)((IData)((((~ ((5U 
                                                 == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4))) 
                                            & (0xe1U 
                                               != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))
                                            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1
                                            : ((0xe1U 
                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                ? 0U
                                                : vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U])))) 
                          << 0x20U) | (QData)((IData)(
                                                      (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)) 
                                                        & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4)) 
                                                           & (0xe1U 
                                                              != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))
                                                        ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__imm
                                                        : 
                                                       ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2)
                                                         ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2
                                                         : 
                                                        ((0xe1U 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))
                                                          ? 
                                                         (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1)
                                                          : 4U)))))) 
                        >> 0x20U)) >> 4U);
    } else {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
            = (0xf7ffffffU & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U]);
    }
    if (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid) 
         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin))) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[0U] 
            = vlSelf->RISCV_BOARD__DOT__inst_sram_addr;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[1U] 
            = (IData)((((QData)((IData)((((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass)) 
                                          & (IData)(vlSelf->RISCV_BOARD__DOT__inst_sram_en))
                                          ? vlSelf->RISCV_BOARD__DOT__inst_sram_rdata
                                          : 0U))) << 0x20U) 
                       | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc))));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
            = (IData)(((((QData)((IData)((((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass)) 
                                           & (IData)(vlSelf->RISCV_BOARD__DOT__inst_sram_en))
                                           ? vlSelf->RISCV_BOARD__DOT__inst_sram_rdata
                                           : 0U))) 
                         << 0x20U) | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc))) 
                       >> 0x20U));
    }
    if (vlSelf->reset) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_cf__DOT__mtvec = 0U;
    } else if ((1U & (~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall)))) {
        if (((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[6U] 
              >> 0x13U) & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid))) {
            if ((0x342U != (0xfffU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
                                      >> 7U)))) {
                if ((0x341U != (0xfffU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
                                          >> 7U)))) {
                    if ((0x305U == (0xfffU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
                                              >> 7U)))) {
                        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_cf__DOT__mtvec 
                            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
                                << 0x19U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] 
                                             >> 7U));
                    } else if (VL_UNLIKELY((0x300U 
                                            != (0xfffU 
                                                & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
                                                   >> 7U))))) {
                        VL_WRITEF("V_WARN[csr write error]\n");
                    }
                }
            }
        }
    }
    if (((IData)(vlSelf->RISCV_BOARD__DOT__inst_sram_en) 
         & (~ (IData)(vlSelf->reset)))) {
        VRISCV_BOARD___024unit____Vdpiimwrap_inst_read_TOP____024unit(vlSelf->RISCV_BOARD__DOT__inst_sram_addr, __Vfunc_inst_read__4__Vfuncout);
        vlSelf->RISCV_BOARD__DOT__inst_sram_rdata = __Vfunc_inst_read__4__Vfuncout;
    }
    if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__mem_valid) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid 
            = (1U & (~ (IData)(vlSelf->reset)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[0U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[0U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[1U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[2U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[2U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[3U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[3U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[4U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[5U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[6U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[6U];
    } else {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[0U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[2U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[3U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[5U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[6U] = 0U;
    }
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__mem_valid 
        = ((~ (IData)(vlSelf->reset)) & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid));
    if (vlSelf->reset) {
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc = 0x7ffffffcU;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid = 0U;
    } else {
        if (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid) 
             & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin))) {
            vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_pc 
                = vlSelf->RISCV_BOARD__DOT__inst_sram_addr;
        }
        if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_allowin) {
            vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid 
                = vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_exe_valid;
        }
    }
    vlSelf->debug_wb_pc = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[3U] 
                            << 0x1eU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[2U] 
                                         >> 2U));
    if ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])) {
        vlSelf->RISCV_BOARD__DOT__data_sram_wmask = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[0U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[1U] = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[2U] = 0U;
    } else {
        vlSelf->RISCV_BOARD__DOT__data_sram_wmask = 
            (0xfU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                     >> 0x14U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                        >> 0xfU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U] 
                        >> 2U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0 
            = (0x1fU & ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                         << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                                   >> 0x1cU)));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[9U] 
                << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                          >> 0x1cU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2 
            = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                          >> 0x1cU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[0U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[0U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[1U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[1U];
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[2U] 
            = vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[2U];
    }
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_store 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                    >> 0x1bU)));
    vlSelf->debug_wb_rf_waddr = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] 
                                          >> 2U));
    vlSelf->debug_wb_rf_wdata = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[4U] 
                                  << 0x1eU) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[3U] 
                                               >> 2U));
    vlSelf->debug_wb_rf_wen = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[6U] 
                                >> 0x14U) & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__wb_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U] 
                    >> 0x18U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                    >> 0x16U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                    >> 0x1aU)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                    >> 0x1bU)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0 
        = (IData)(((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[9U] 
                    >> 0x1bU) & (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 0xdU)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 5U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 6U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu 
        = (1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                    >> 7U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass 
        = ((IData)(((vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U] 
                     >> 0x19U) & (~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])))
            ? ((1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                      & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                         >> 0x15U))) ? vlSelf->RISCV_BOARD__DOT__data_sram_rdata
                : ((1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                          & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                             >> 0x14U))) ? (((- (IData)(
                                                        ((vlSelf->RISCV_BOARD__DOT__data_sram_rdata 
                                                          >> 0xfU) 
                                                         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0)))) 
                                             << 0x10U) 
                                            | (0xffffU 
                                               & vlSelf->RISCV_BOARD__DOT__data_sram_rdata))
                    : ((1U & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                              & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                                 >> 0x13U))) ? (((- (IData)(
                                                            ((vlSelf->RISCV_BOARD__DOT__data_sram_rdata 
                                                              >> 7U) 
                                                             & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT____VdfgTmp_h0c27a012__0)))) 
                                                 << 8U) 
                                                | (0xffU 
                                                   & vlSelf->RISCV_BOARD__DOT__data_sram_rdata))
                        : 0U))) : ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                    ? 0U : ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U] 
                                             << 0xdU) 
                                            | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U] 
                                               >> 0x13U))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load)) 
                 & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                    & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                       >> 0x19U))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub) 
           | ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt) 
              | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu)));
    __Vtemp_h10a86387__0[5U] = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                           ? 0ULL : 
                                          (0x3ffffffffULL 
                                           & (((QData)((IData)(
                                                               vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U])) 
                                               << 9U) 
                                              | ((QData)((IData)(
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U])) 
                                                 >> 0x17U))))) 
                                 << 0x13U) | (((IData)(
                                                       ((1U 
                                                         & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                         ? 0ULL
                                                         : 
                                                        (0x1ffffffffffffULL 
                                                         & (((QData)((IData)(
                                                                             vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U])) 
                                                             << 0x1eU) 
                                                            | ((QData)((IData)(
                                                                               vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])) 
                                                               >> 2U))))) 
                                               >> 0x1eU) 
                                              | ((IData)(
                                                         (((1U 
                                                            & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                                            ? 0ULL
                                                            : 
                                                           (0x1ffffffffffffULL 
                                                            & (((QData)((IData)(
                                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U])) 
                                                                << 0x1eU) 
                                                               | ((QData)((IData)(
                                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])) 
                                                                  >> 2U)))) 
                                                          >> 0x20U)) 
                                                 << 2U)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[3U] 
        = ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass 
            << 2U) | ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                       ? 0U : (3U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[4U] 
        = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                      ? 0ULL : (0x1ffffffffffffULL 
                                & (((QData)((IData)(
                                                    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[4U])) 
                                    << 0x1eU) | ((QData)((IData)(
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[3U])) 
                                                 >> 2U))))) 
            << 2U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass 
                      >> 0x1eU));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[5U] 
        = __Vtemp_h10a86387__0[5U];
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_wb_bus[6U] 
        = (((IData)(((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                      ? 0ULL : (0x3ffffffffULL & (((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U])) 
                                                   << 9U) 
                                                  | ((QData)((IData)(
                                                                     vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U])) 
                                                     >> 0x17U))))) 
            >> 0xdU) | ((IData)((((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                                   ? 0ULL : (0x3ffffffffULL 
                                             & (((QData)((IData)(
                                                                 vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[6U])) 
                                                 << 9U) 
                                                | ((QData)((IData)(
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_stage__DOT__exe_to_mem_bus_r[5U])) 
                                                   >> 0x17U)))) 
                                 >> 0x20U)) << 0x13U));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin)
            ? ((1U & vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U])
                ? 0xffffffffU : (~ ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[8U] 
                                     << 4U) | (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[7U] 
                                               >> 0x1cU))))
            : vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result 
        = (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
           + (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b 
              + (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__dst_load) 
           & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result 
        = (((- (IData)((1U & (((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                               & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                  >> 4U)) | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sub))))) 
            & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result) 
           | ((1U & ((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_slt))) 
                     & (((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0)) 
                         & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0)) 
                        | ((~ ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0) 
                               ^ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h25d289c6__0))) 
                           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_result 
                              >> 0x1fU))))) | ((1U 
                                                & ((- (IData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sltu))) 
                                                   & (~ (IData)(
                                                                (1ULL 
                                                                 & (((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1)) 
                                                                     + 
                                                                     ((QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_b)) 
                                                                      + (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__adder_cin)))) 
                                                                    >> 0x20U)))))) 
                                               | (((- (IData)(
                                                              (1U 
                                                               & ((~ 
                                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                  & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                     >> 8U))))) 
                                                   & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                      & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2)) 
                                                  | (((- (IData)(
                                                                 (1U 
                                                                  & ((~ 
                                                                      vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                     & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                        >> 9U))))) 
                                                      & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                         | vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2)) 
                                                     | (((- (IData)(
                                                                    (1U 
                                                                     & ((~ 
                                                                         vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                        & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                           >> 0xaU))))) 
                                                         & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                            ^ vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2)) 
                                                        | (((- (IData)(
                                                                       (1U 
                                                                        & ((~ 
                                                                            vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                              >> 0xeU))))) 
                                                            & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src2) 
                                                           | (((- (IData)(
                                                                          (1U 
                                                                           & ((~ 
                                                                               vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                              & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                                >> 0xbU))))) 
                                                               & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1 
                                                                  << (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0))) 
                                                              | ((- (IData)(
                                                                            (1U 
                                                                             & (((~ 
                                                                                vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                                                                & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[5U] 
                                                                                >> 0xcU)) 
                                                                                | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra))))) 
                                                                 & (IData)(
                                                                           ((((QData)((IData)(
                                                                                (- (IData)(
                                                                                ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT__op_sra) 
                                                                                & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h9dbf4c0d__0)))))) 
                                                                              << 0x20U) 
                                                                             | (QData)((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_src1))) 
                                                                            >> (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_alu__DOT____VdfgTmp_h255a08e4__0))))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_to_id_valid 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
           & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_exe_valid 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
           & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid)) 
                 | ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
                    & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_allowin))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass 
        = (1U & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U] 
                 | ((((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result) 
                      & ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                         & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                            >> 3U))) | ((~ vlSelf->RISCV_BOARD__DOT__cpu__DOT__wb_stage__DOT__mem_to_wb_bus_r[1U]) 
                                        & ((vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__id_to_exe_bus_r[4U] 
                                            >> 2U) 
                                           & vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result))) 
                    & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__exe_valid))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_valid)) 
                 | ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_if_loadbypass)) 
                    & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_allowin))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_identIMM__DOT____VdfgTmp_h78278846__0 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
           & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
              >> 0x1fU));
    if (vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass) {
        vlSelf->__VdfgTmp_hea37eb48__0 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3 = 0U;
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op = 0U;
    } else {
        vlSelf->__VdfgTmp_hea37eb48__0 = (0x1fU & (
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                                   >> 7U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                        >> 0x14U));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                        >> 0xfU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3 
            = (7U & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                     >> 0xcU));
        vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op 
            = (0x1fU & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                        >> 2U));
    }
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak 
        = (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
                 & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                    >> 0x14U)));
    vlSelf->RISCV_BOARD__DOT__inst_sram_en = ((~ (IData)(vlSelf->reset)) 
                                              & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__if_stage__DOT__if_allowin));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass) 
            & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass) 
                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2)) 
               & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))))
            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result
            : (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass) 
                & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass) 
                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2)) 
                   & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))))
                ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass
                : (((IData)(vlSelf->debug_wb_rf_wen) 
                    & (((IData)(vlSelf->debug_wb_rf_waddr) 
                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2)) 
                       & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))))
                    ? vlSelf->debug_wb_rf_wdata : (
                                                   (0U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2))
                                                    ? 0U
                                                    : 
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf
                                                   [vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs2]))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rfwenbypass) 
            & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_rdbypass) 
                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1)) 
               & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))))
            ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_stage__DOT__alu_result
            : (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rfwenbypass) 
                & (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_rdbypass) 
                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1)) 
                   & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))))
                ? vlSelf->RISCV_BOARD__DOT__cpu__DOT__mem_to_id_bypass
                : (((IData)(vlSelf->debug_wb_rf_wen) 
                    & (((IData)(vlSelf->debug_wb_rf_waddr) 
                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1)) 
                       & (0U != (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))))
                    ? vlSelf->debug_wb_rf_wdata : (
                                                   (0U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1))
                                                    ? 0U
                                                    : 
                                                   vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_rf__DOT__rf
                                                   [vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rs1]))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op) 
            << 4U) | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3) 
                       << 1U) | (1U & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
                                       & (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U] 
                                          >> 0x1eU)))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3 
        = (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op) 
            << 3U) | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__func3));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2 
        = (vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata1 
           == vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__rdata2);
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_ecall 
        = ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op_ebreak)) 
           & (0x1c0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__dst_store 
        = ((0x40U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
           | ((0x41U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
              | (0x42U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_4 
        = ((0x1bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
           | (0xc8U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt 
        = ((0xc4U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
           | (0xc6U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb 
        = ((0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
           & ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass)) 
              & vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__if_to_id_bus_r[2U]));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0 
        = ((((0xc0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
             & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2)) 
            | ((~ (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__branch_rs1_eq_rs2)) 
               & (0xc1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)))) 
           | (0x1bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__src2_is_rs2 
        = ((0xc0U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
           | ((0xc1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
              | ((0xc2U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                 | ((0xc4U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                    | ((0xc6U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                       | ((0xc8U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                          | ((0xcaU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                             | ((0xcbU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                | ((0xccU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                   | ((0xceU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                      | ((0xc5U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                         | ((0xc7U 
                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                            | (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_branch_blt)))))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__alu_op 
        = ((((0xdU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
             | (0xe1U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
            << 0xaU) | ((((0xcbU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                          | (0x4bU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37))) 
                         << 9U) | ((((0xcaU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                     | (0x4aU == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37))) 
                                    << 8U) | ((((0xc2U 
                                                 == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                | (0x42U 
                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37))) 
                                               << 7U) 
                                              | ((((0xc8U 
                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                   | (0x24U 
                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                  << 6U) 
                                                 | ((((0xccU 
                                                       == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                      | (0x26U 
                                                         == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                     << 5U) 
                                                    | ((((0xceU 
                                                          == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                         | (0x27U 
                                                            == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
                                                        << 4U) 
                                                       | ((((0xc6U 
                                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                            | ((0x23U 
                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                               | ((0xc7U 
                                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                  | (0xc6U 
                                                                     == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))) 
                                                           << 3U) 
                                                          | ((((0xc4U 
                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                               | ((0x22U 
                                                                   == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                  | ((0xc5U 
                                                                      == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                     | (0xc4U 
                                                                        == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))))) 
                                                              << 2U) 
                                                             | (((0xc1U 
                                                                  == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                                 << 1U) 
                                                                | ((0xc0U 
                                                                    == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op37)) 
                                                                   | ((0x20U 
                                                                       == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                      | ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_dec__DOT__inst_lb) 
                                                                         | ((4U 
                                                                             == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                            | ((1U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                               | ((5U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((2U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x40U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x41U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x42U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | ((0x1bU 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op)) 
                                                                                | ((0xc8U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3)) 
                                                                                | (5U 
                                                                                == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__op))))))))))))))))))))))));
    vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_to_if_brjmpbypass 
        = ((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__exe_to_id_brjmpbypass) 
           | (((IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____VdfgTmp_h141f93ed__0) 
               | (0xc8U == (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT____Vcellinp__id_dec__op3))) 
              & (IData)(vlSelf->RISCV_BOARD__DOT__cpu__DOT__id_stage__DOT__id_valid)));
}
